Conventionally, many computers employ the “virtual storage method”. The “virtual storage method” is a technology that makes a memory capacity greater than an actual memory capacity in a computer appear to be provided on the computer by using an external memory device (e.g., a hard disk device) as a save area of a memory. Thus, when the memory capacity becomes insufficient, the “virtual storage method” temporarily saves less-frequently-used information among information on the memory to a swap area that has been secured within the hard disk device by an OS, to temporarily compensate for the insufficiency in the memory capacity.
In the “virtual storage method”, two addresses, a virtual address (VA) and a physical address (PA), are used. When an application side performs reading and writing (memory access) with respect to a memory, a virtual address is used. A physical address is an address assigned to a component of a memory. For the purpose of translating a virtual address into a physical address, a computer employing the virtual storage method, stores a list (hereinafter referred to as “page table”) of address translation pairs (translation table entry: TTE) for translating virtual addresses into physical addresses.
Normally, the page table is stored in a translation storage buffer (TSB) area of a main memory. However, if a central processing unit (CPU) is to refer to the page table stored in the main memory every time a translation from a virtual address (TTE-tag) into a physical address (TTE-data) is required, since access from the CPU to the main memory cannot be fast, a longer period of time is to be spent on the translation. To avoid this, normally, a cache memory dedicated to address translation and referred to as a translation-lookaside buffer (TLB) or address translation buffer is installed inside the CPU. The TLB stores some of the address translation pairs from the page table stored in the TSB area.
To perform a memory access with such a configuration, the CPU first searches the TLB. For the TLB search, the CPU uses a virtual address and a context ID (a unique ID for each process). If the values used for the TLB search and values stored in the TLB match each other with respect to these two, it is assumed that an address translation result is present in the TLB, and the CPU obtains the address translation result. When the address translation result corresponding to the requested address and context ID is present in the TLB, it is called a TLB hit. When not present, it is called a TLB miss (memory management unit-MISS: MMU-MISS). When a TLB miss occurs, an MMU-MISS-TRAP is generated. The CPU thus reports the generation of MMU-MISS-TRAP to the OS and the OS that has been reported performs a trap handling process with respect to the CPU.
Conventional technologies (mainly related to the trap handling process) disclosed in Japanese Laid-open Patent Publication No. 2007-122667 and Japanese Laid-open Patent Publication No. 07-200409 are described with reference to FIG. 7. FIG. 7 is a diagram for explaining the conventional technologies. Inherently, a memory access process performed by the CPU is branched depending on a plurality of determinations during the process. However, for convenience in clearly explaining differences between (A) and (B), in FIG. 7, the process is illustrated without determinations and a distinguishing a normal trap handling process from other processes. In FIG. 7, the portion surrounded by a rectangle indicates steps common between (A) and (B).
First, the description is given regarding (A) in FIG. 7. If, during a memory access, the CPU fails in the TLB search (TLB miss) with a certain virtual address specified by the OS, then an MMU-MISS-TRAP is generated in the CPU (see (1)). The CPU then reports the MMU-MISS-TRAP to the OS, and thus the OS performs a trap handling process for the CPU. Specifically, the CPU sets the certain virtual address, for which the MMU-MISS-TRAP has been generated, in a register (see (2)). Then, based on the virtual address, the CPU generates a TSB virtual address that corresponds to the virtual address (see (3)). Herein, a TSB virtual address is a virtual address in the TSB area storing an address translation pair corresponding to the virtual address. The CPU sets the generated TSB virtual address in the register (See (4)).
Then, the CPU reads the virtual address and the TSB virtual address set in the register from the register (see (5)) and searches the TLB for an address translation pair of the TSB virtual address and a TSB physical address (TSB pointer) corresponding to the TSB virtual address (see (6)). The CPU then search a cache memory using the TSB physical address retrieved from the TLB (see (7)).
Herein, it is assumed that an address translation pair (address translation pair of the virtual address and the physical address) is not retrieved as a result of searching the cache memory (i.e., that a cache miss occurs). Thus, the CPU searches a main memory using the TSB physical address retrieved from the TLB (see (8)), reads the corresponding address translation pair from the main memory, and registers it in the cache memory (See (9)).
Subsequently, the CPU again searches the TLB for the address translation pair of the TSB virtual address and the TSB physical address corresponding to the TSB virtual address (see (10)). The CPU then searches the cache memory using the TSB physical address retrieved from the TLB (see (11)). Since the address translation pair is retrieved as a result of searching the cache memory (i.e., since the address translation pair is already registered in the cache memory at (9), cache miss does not occur), the CPU reads the address translation pair from the cache memory and registers it in the TLB (see (12)). In this way, when the CPU searches the TLB again for the certain virtual address, there is going to be a TLB hit.
Due to the cache miss occurring at (8) in the steps at (A) described above, the CPU needs to repeat the steps of (10) and (11) again. Thus, a penalty (such as delay) upon a cache miss is big. Accordingly, in Japanese Laid-open Patent Publication No. 2007-122667 a technique is proposed, as illustrated in which, apart from a normal trap handling process, the CPU searches the main memory using the TSB physical address retrieved from the TLB, obtains the address translation pair from the main memory, and pre-fetches the obtained address translation pair in the cache memory, as illustrated at (7) at (B) in FIG. 7.
In the abovementioned conventional technology, the penalty upon a TLB miss is still big as explained below. That is, in the conventional technology, the CPU still consumes time in the process of obtaining the address translation pair of the virtual address and the physical address from the TSB area of the main memory and pre-fetching that address translation pair in the cache memory. Specifically, in the conventional technology, for the CPU to obtain the address translation pair from the TSB area, the TSB physical address can be searched from the TLB, and this search consumes time. Moreover, the TSB virtual address can be calculated in the conventional technology, and the complexity in the calculation of the TSB virtual address results in an increase in the circuit scale and the installation cost.